The field of the invention is directed to a method of manufacturing a semiconductor device or a plurality of semiconductor devices in an integrated circuit. More particularly, the invention relates to a novel method of planarizing the surface of an integrated circuit which results in the improved hermetic sealing and scratch protection of the underlying circuitry in the integrated circuit.
The manufacturing processes used for making integrated circuits often involve the formation of various layers upon a semiconductor substrate. For example, the use of multilayer structures such as dual layer metal interconnects to improve the speed of the "metal-oxide-semiconductor" (MOS) semiconductor devices on the integrated circuit is becoming more wide spread. One of the last layers which is applied to the upper surface of the integrated circuit is usually a passivation layer, which in some cases may actually be a plurality of layers applied to make the surface of the integrated circuit less rugged and hence more planar. The passivation layer of the integrated circuit protects, as it is well known, the integrated circuit from the environment including protection against alpha particles, against water and other deleterious substances. Moreover, the passivation reduces the capacitance of the various devices through a field effect.
The passivation layer (or layers) tends to undergo increased stress as the surface topology of the integrated circuit becomes increasingly more complex with many sharp edges and steps. When the surface topology becomes rugged, the passivation layer tends to form weakened areas, particularly where the passivation is thinned or near keyholes such as the keyhole 6 shown in FIG. 1c. Keyholes, such as the keyhole 6, are voids in the passivation layer 5 (layers).
As the number of layers increase, the steps and differences in height between the levels of adjacent layers increase, resulting in the varying thickness of the layers (e.g. passivation layers) deposited on top of these underlying layers. FIG. 1a shows, by a cross sectional representation, an example of the surface topology of an integrated circuit or semiconductor device which may be found in the prior art. Two conductors 2 and 3 run over a field oxide region 1. These two conductors 2 and 3 typically serve to carry the signals through an integrated circuit and they also cause the surface to have many sharp edges, steps and abrupt contours. FIG. 1a shows the upper surface of an integrated circuit where the conductors 2 and 3 have been applied over a field oxide region 1. These conductors often have a height as small as one micron as shown in FIG. 1a. Following the formation of the conductors 2 and 3, a thin low temperature oxide (LTO), which is a dielectric, is layered upon the surface of the integrated circuit thereby covering the conductors 2 and 3 and the field oxide region 1. As shown in FIG. 1b, a layer of low temperature oxide (LTO) 4 has been deposited over the surface of the conductors 2 and 3 and the field oxide region 1. Then, as shown in FIG. 1c a passivation layer 5 has been applied over the surface of the low temperature oxide 4. It can be seen that the variations in the height of the integrated circuit cause the passivation layer 5 to have a more rugged surface which is more likely to produce problems than a smoother surface. If, for example, the passivation layer 5 becomes very thin at a step, breaking and/or cracking of this layer at this step is likely to occur during further processing and/or thermal stressing. Moreover, keyholes often form in "valleys" between tall objects (which are adjacent but spaced apart) on the surface of the integrated circuit. For example, the keyhole 6 shown in FIG. 1c is an area of the integrated circuit where the passivation layer is prone to cracking. This, of course, destroys the effectiveness of this passivation layer which is used to protect the integrated circuit from the ambient. The ruggedness of the surface topology increases as the conductors 2 and 3 are spaced closer together to increase the amount of circuitry contained on each integrated circuit chip.
The passivation layers are often deposited onto the upper surface of the integrated circuit containing the semiconductor devices using well known low temperature and low pressure chemical vapor deposition techniques. Among the materials used for the passivation layers are silicon dioxide (SiO.sub.2) and siliconitride (Si.sub.3 N.sub.4), or some combination of these compounds, which are referred to as oxynitrides. Although these passivation layers are known to produce conformal coatings for widely flat surfaces, they fall short of producing adequate coverage of the rugged topology as the integrated circuit density and complexity increase. As a result, voiding (e.g. the formation of a keyhole) in the passivation layers occurs which poses a reliability concern. This is shown schematically in FIG. 1c, which shows the keyhole 6.
Various techniques in the prior art of topographical planarization are used to overcome these problems. The techniques for topographical planarization must satisfy certain requirements to assure the reliability of the integrated circuits ("ICs"). These requirements include (1) the use of low temperature processing since the planarization must be compatible with the underlying aluminum interconnections (connecting components of the IC) such as conductors 2 and 3; (2) no adverse effects on the electrical properties of the underlying circuitry; (3) ease of manufacturability; (4) high reliability; and (5) high transmittance to ultraviolet radiation for programmable semiconductor devices such as EPROMs (Eraseable Programmable Read Only Memory).
Many methods in the prior art are available for low temperature planarization, such as the methods described in the papers reported in the 1986 Proceedings Third International IEEE VLSI Multilevel Interconnection Conference (1986). These methods include sacrificial etchback using photoresist, bias sputtered quartz and planarization using polyimide films. Spin-on-glass planarization is preferred over these other techniques because of its ease of implementation in large volume device manufacturing and also because it satisfies many of the aforementioned requirements/criteria. For example, polyimide films cannot be used because it blocks ultraviolet radiation which is used to erase EPROMs.
Spin-on-glass is a silicon containing polymer which is dissolved in alcohol-based solvents. This material is in the liquid form and can be applied onto wafers on which are built the semiconductor devices by spinning a few milliliters at high RPMs (revolutions per minute) over the upper surface of the wafers, which normally include a plurality of "chips" (integrated circuits). The planarizing ability of spin-on-glass (SOG) stems from the fact that the SOG as applied in the liquid form, fills the gaps and voids ("Valleys") on the surface, and thins down considerably during spinning as the material is swept across the high points on the surface of the integrated circuit. After spinning the SOG over the integrated circuit, the SOG is hardened into a solid in a process referred to as curing. With straight forward and well known curing in conventional furnaces for about 30 minutes, the spin-on-glass material loses most of its solvents and converts into silicon dioxide, although the silicon dioxide is contaminated with various substances (e.g. sodium). There are many methods for using spin-on-glass to planarize the surface of integrated circuits.
The most straight forward application in the prior art of spin-on-glass planarization is to use the SOG material directly on the top of the integrated circuit, which usually includes the conductors which run across the top of the integrated circuit to interconnect the various components (e.g. MOS devices) in the integrated circuit. Hence, the SOG material is deposited directly over the surface of the integrated circuit as shown in FIG. 1a to cover the conductors 2 and 3. The SOG is in direct contact with the conductors 2 and 3 and the FOX 1 layer. Following the spinning and curing of the spin-on-glass, a thick passivation layer 5 is deposited on the top of the SOG. The resulting structure is substantially as shown in FIG. 3d except that there is no LTO 4 layer in the resulting structure. One serious limitation in this regard is that the SOG thickness can be relatively substantial in the "valleys", such as the space between the metal interconnects (conductors), which results in a number of failures such as cracking of the SOG film. Additionally, the adhesion of the SOG material to the bare metal lines becomes a major failure mode. Therefore, sandwich structures such as low temperature oxide/SOG combinations are preferred.
FIGS. 3a through 3d show a prior art planarization technique utilizing a sandwich structure of low temperature oxide and SOG. Beginning with FIG. 3a, conductors 2 and 3 are applied upon the layer 1, which is often an oxide used to isolate the conductors. This is shown in FIG. 3a. A thin film of low temperature oxide 4 (e.g. silicon dioxide deposited by low temperature chemical vapor deposition) is deposited over the surface of the integrated circuit thereby covering the conductors 2 and 3 and the layer 1 as shown in FIG. 3b. Next, the SOG material is spun on the integrated circuit and cured (in conventional furnaces ("ovens") for 30 minutes at 400.degree. C.) at low temperatures to assure the integrity of the conductors 2 and 3. Following this prior art type of curing, the structure shown in FIG. 3c is produced. Next, the final passivation film 5 is deposited on this highly iso-planar surface which is shown in cross section in FIG. 3d.
A variation in the prior art of this planarization technique includes an etch-back step before the final passivation layer is deposited, and this variation is shown by FIGS. 4a through 4e. As described above, the conductors 2 and 3 are deposited upon the layer 1 to form the structure shown in FIG. 4a. Then, a layer of low temperature oxide 4 is formed upon the surface of the integrated circuit shown in FIG. 4a to thereby form the structure shown in FIG. 4b. The SOG layer is then applied by spinning SOG (in the liquid form) onto the surface of the IC and then curing the SOG material in conventional furnaces kept at 400.degree. C. for 30 minutes to form the structure as shown in FIG. 4c. The variation in the technique is usually done by dry etching (plasma etching) the structure shown in FIG. 4c to remove the very thin spin-on-glass 11 from the high points and a small amount of the low temperature oxide 4 from the high points on the integrated circuit, such as the top of the LTO layer 4 immediately above the top of the conductors 2 and 3. This dry etching step (referred to as an "etch-back") produces the structure shown in FIG. 4d where the areas at lower elevations (e.g. a valley) still contain both the spin-on-glass 11 and the LTO 4, as shown in FIG. 4d. The etch-back step is performed following the application of the SOG layer 11 shown in FIG. 4c. FIG. 4d shows that a portion of the LTO 4 has been removed from the highest elevations of the integrated circuit and a portion of the SOG 11 layer near the top of the integrated circuit has been removed. A final passivation layer 5 is then applied upon the integrated circuit shown in FIG. 4d to produce the structure shown in FIG. 4e.
In these prior art planarization techniques, such as those shown in FIGS. 3a-3d and FIGS. 4a-4e, some SOG remains, particularly in the case of the processing described with respect to FIGS. 3a-3d. A major drawback of these planarization techniques utilizing SOG is the lack of reliability of the devices manufactured in these ways. Spin-on-glass materials are organic based and contain to some extent mobile ions, such as sodium ions, which are detrimental to the transistors used in the integrated circuits. Also, the hygroscopicity (water absorption and retention) of these materials is high such that they induce corrosion of the metal lines (conductors) during the lifetime of the device. Therefore, it is desirable to remove all of the SOG material from the integrated circuit surface without losing the advantage gained from planarizing the surface with SOG material.
Thus, it is an object of the invention to provide an improved technique for planarizing the surface of an integrated circuit while also providing adequate passivation through a passivation layer. It is also an object of the invention to provide a technique for planarization, which technique removes all the spin-on-glass material prior to final passivation but uses the SOG material to improve planarization of the passivation surface.